In the field of data processing apparatus that can execute various virtual processors the control and routing of interrupts to the virtual processors can be complicated and can require a large number of cycles to resolve. Conventionally in a system with multiple processors executing at one time, some of which are virtual processors, a hypervisor controls the interrupts and determines where to send them.
Conventionally this has been done using an interrupt translation table, which defines the ID of the interrupt seen by the software and the processor to which the interrupt should be sent. Where there is an interrupt to a virtual processor, the table maps the received virtual interrupt to a physical interrupt. The hypervisor then needs to do the reverse mapping and may then have to schedule the virtual machine if it is not currently active. This reverse mapping has generally required a large number of cycles. Furthermore, where there are many virtual processors, the interrupt translation table that stores these mappings can be very large.
It would be desirable to be able to handle virtual interrupts with a lower software performance overhead and without the need to store large amounts of data.